Finfet with merge-free fins

ABSTRACT

A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions.

DOMESTIC PRIORITY

This application is a division of U.S. patent application Ser. No.13/965,322, filed Aug. 13, 2013, which is a continuation of U.S. patentapplication Ser. No. 13/713,842, filed Dec. 13, 2012, the disclosures ofwhich are incorporated by reference herein in their entireties.

BACKGROUND

The invention relates to a semiconductor device, and more particularly,to patterning fins of a FinFET semiconductor device.

Interests in multi-gate MOSFETs have significantly increased as theindustry continues to demand smaller sized MOSFET devices. One suchdevice that is capable of maintaining industry performance standards ata reduced size is the FinFET.

A conventional FinFET includes one or more fins that are patterned on asubstrate, such as a silicon-on-insulator (SOI). For example, aconventional sidewall image transfer (SIT) process can be used to form adense array of fins, which extend into the source/drain (S/D) regions ofthe FinFET. Conventional FinFET fabrication requires an epitaxy (EPI)process to merge the fins formed in the S/D regions. However, thisprocess causes undesirable gaps between the fins, and may also createsource/drain shorting issues at the gate line ends if the EPI process isnot properly controlled.

Moreover, conventional fabrication processes perform gate patterning forforming a gate after forming the fins. The gate patterning utilizeshardmasks, and performs additional spacer etching processes. However,the fins may be inadvertently eroded during the gate and spacer etchingprocesses.

SUMMARY

According to an exemplary embodiment, a semiconductor device having agate region comprises an insulation layer extending along a firstdirection to define a length and a second direction perpendicular to thefirst direction to define a width. The insulation layer has a gateinsulation region disposed between first and second non-gate insulationregions that are different from the gate insulation region. An activesemiconductor layer is formed on an upper surface of the insulationlayer, and a plurality of fins is formed on the gate and spacer regionsand between the first and second non-gate insulation regions.

In another exemplary embodiment, a semiconductor device has first andsecond non-gate regions. The semiconductor device comprises asemiconductor substrate including an active semiconductor layer disposedon an insulation layer, and has a gate pocket formed between the firstand second non-gate regions. The gate pocket extends through the activesemiconductor layer and the insulation layer to define a recessed gateinsulation region. A plurality of fins are supported by walls of therecessed gate insulation region and are disposed a predetermineddistance above the recessed gate insulation layer to define a voidbeneath each fin among the plurality of fins.

In yet another exemplary embodiment, a method of fabricating asemiconductor device comprises forming an insulation layer having alength extending along a first direction and a width extending along asecond direction perpendicular to the first direction. The insulationlayer has a gate insulation region located between first and secondnon-gate insulation regions. The method further includes forming anactive semiconductor layer on an upper surface of the insulation layer,and forming a plurality of fins at the gate and spacer regions andbetween the first and second non-gate insulation regions.

In still another exemplary embodiment, a method of forming asemiconductor device having first and second non-gate regions comprisesforming an active semiconductor layer disposed on an insulation layer,forming a gate pocket through the active semiconductor layer and theinsulation layer to define a recessed gate insulation region between thefirst and second non-gate regions, forming a plurality of fins supportedby walls of the gate pocket. The method further includes removing aportion of the recessed gate insulation region located beneath theplurality of fins to define a void between each fin among the pluralityof fins and the recessed gate insulation region.

In still another exemplary embodiment of the present teachings, a methodof fabricating a semiconductor device comprises forming a semiconductorsubstrate including a plurality of layers and having a gate regionlocated between first and second non-gate regions that are differentfrom the gate region. The method further includes forming a gate pocketat the gate region that extends through the plurality of layers, andforming a plurality of fins in the gate pocket such that each fin amongthe plurality of fins is isolated from the first and second non-gateregions.

In another exemplary embodiment, a method of fabricating semiconductordevice comprises forming an insulation layer having a length extendingalong a first direction and a width extending along a second directionperpendicular to the first direction. The insulation layer has a gateinsulation region disposed between first and second non-gate insulationregions. The method further includes forming an active semiconductorlayer on an upper surface of the insulation layer. The method furtherincludes forming a plurality of fins at the gate insulation region andbetween the first and second non-gate insulation regions.

In still another embodiment, a method of forming a semiconductor devicehaving first and second non-gate regions comprises forming an activesemiconductor layer disposed on an insulation layer. The method furtherincludes forming a gate pocket through the active semiconductor layerand the insulation layer to define a recessed gate insulation regionbetween the first and second non-gate regions. The method furtherincludes forming a plurality of fins supported by walls of the gatepocket. The method further includes removing a portion of the recessedgate insulation region located beneath the plurality of fins to define avoid between each fin among the plurality of fins and the recessed gateinsulation region.

Additional features and utilities are realized through the techniques ofthe present teachings. Other exemplary embodiments and features of theteachings are described in detail herein and are considered a part ofthe claimed teachings. For a more detailed description of the teachingsand features, drawings and descriptions of the exemplary embodiments arepresented below.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The subject matter describing exemplary embodiments of the teachings isparticularly pointed out and distinctly claimed in the claims at theconclusion of the specification. The forgoing and other features, andutilities of the teachings are apparent from the following detaileddescription taken in conjunction with the accompanying drawings inwhich:

FIGS. 1-27 are a series of views illustrating a method of forming afinFET device according to exemplary embodiments of the presentteachings, in which:

FIG. 1A is a top view illustrating a SiO₂ masking layer formed atop astarting substrate;

FIG. 1B is a cross sectional view of the starting substrate illustratedin FIG. 1A taken along the lines A-A′ illustrating the formation of theSiO₂ masking layer atop an SOI layer;

FIG. 2 is a cross sectional view illustrating patterning of the SiO₂masking layer to form a gate pocket;

FIG. 3 is a top view of the structure of FIG. 2, following transfer ofthe SiO₂ masking layer patterning into the SOI layer to definesemiconductor fins in the gate pocket;

FIG. 4A is a cross sectional view in a first orientation taken along thelines A-A′ of FIG. 3;

FIG. 4B is a cross sectional view in a second orientation taken alongthe lines B-B′ of FIG. 3;

FIG. 5A is a cross sectional view in the first orientation illustratingthe formation of a spacer layer over the device shown in FIG. 4A;

FIG. 5B is a cross sectional view in the second orientation illustratingthe formation of the spacer layer over the device shown in FIG. 5A;

FIG. 6A is a cross sectional view in the first orientation illustratingthe partial etching of the spacer layer shown in FIG. 5A;

FIG. 6B is a cross sectional view in the second orientation illustratingthe partial etching of the spacer layer shown in FIG. 6A;

FIG. 7A is a cross sectional view in the first orientation, following adeposition of amorphous/polysilicon gate material in the gate pocket ofthe device illustrated in FIG. 6A;

FIG. 7B is cross sectional view in the second orientation of theamorphous/polysilicon gate material deposited in the gate pocket of thedevice illustrated in FIG. 7A;

FIG. 8A is a cross sectional view in the first orientation of the deviceillustrated in FIG. 7A, following removal of the SiO₂ masking layer;

FIG. 8B is cross sectional view in the second orientation, following theremoval of the SiO₂ masking layer illustrated in FIG. 8A;

FIG. 9A is cross sectional view in the first orientation illustrating anextension ion implantation of the device shown in FIG. 8A;

FIG. 9B is a cross sectional view in the second orientation illustratingthe extension implantation of the device shown in FIG. 9A;

FIG. 10A is a cross sectional view in the first orientation, followingdeposition of a second spacer on the device shown in FIG. 9A;

FIG. 10B is a cross sectional view in the second orientationillustrating the deposition of the second spacer shown on the device ofFIG. 10A;

FIG. 11A is cross sectional view in the first orientation illustratingsource/drain ion implantation of the device shown in FIG. 10A;

FIG. 11B is a cross sectional view in the second orientationillustrating the source/drain implantation of the device shown in FIG.11A;

FIG. 12A is a cross sectional view in the first orientation, following aformation of a second SiO₂ hard mask formed on the device shown in FIG.11A;

FIG. 12B is a cross sectional view in the second orientation of thesecond SiO₂ hard mask on the device shown in FIG. 12A;

FIG. 13A is a cross sectional view in the first orientation followingremoval of the amorphous/polysilicon gate material to expose the gatepocket of the device illustrated in FIG. 12A;

FIG. 13B is a cross sectional view in the second orientation followingthe removal of the amorphous/polysilicon gate material the deviceillustrated in FIG. 13A;

FIG. 14A is a cross sectional view in the first orientation, following adeposition of high-k and metal gate material in the gate pocket of thedevice illustrated in FIG. 13A;

FIG. 14B is cross sectional view in the second orientation of the high-kand metal gate material deposited in the gate pocket of the deviceillustrated in FIG. 14A;

FIG. 15A is a cross sectional view in the first orientation afterrecessing the buried oxide layer below the semiconductor fins of thedevice illustrated in FIG. 3A according to another exemplary embodimentof the present teachings;

FIG. 15B is a cross sectional view in the second orientationillustrating the buried oxide layer below the semiconductor fins of thedevice illustrated in FIG. 15A;

FIG. 16A is a cross sectional view in the first orientation illustratingthe formation of a spacer layer over the device shown in FIG. 15A;

FIG. 16B is a cross sectional view in the second orientationillustrating the formation of the spacer layer over the device shown inFIG. 16A;

FIG. 17A is a cross sectional view in the first orientation illustratingthe partial etching of the spacer layer shown in FIG. 16A;

FIG. 17B is a cross sectional view in the second orientationillustrating the partial etching of the spacer layer shown in FIG. 17A;

FIG. 18A is a cross sectional view in the first orientation illustratingremoval of the buried oxide layer beneath the fins shown in FIG. 17A toform hanging fins;

FIG. 18B is a cross sectional view in the second orientationillustrating the removal of the buried oxide layer to form the hangingfins of the device shown in FIG. 18A;

FIG. 19A is a cross sectional view in the first orientation, followingan annealing process performed on the hanging fins shown in FIG. 18A toform nanowire fins;

FIG. 19B is a cross sectional view in the second orientationillustrating the nanowire fins of the device shown in FIG. 19A;

FIG. 20A is a cross sectional view in the first orientation, following adeposition of amorphous/polysilicon gate material in the gate pocket ofthe device illustrated in FIG. 19A;

FIG. 20B is cross sectional view in the second orientation of theamorphous/polysilicon gate material deposited in the gate pocket of thedevice illustrated in FIG. 20A;

FIG. 21A is a cross sectional view in the first orientation, followingremoval of the SiO₂ masking layer shown in FIG. 20A;

FIG. 21B is cross sectional view in the second orientation, followingthe removal of the SiO₂ masking layer illustrated in FIG. 21A;

FIG. 22A is cross sectional view in the first orientation illustratingan extension ion implantation of the device shown in FIG. 21A;

FIG. 22B is a cross sectional view in the second orientationillustrating the extension implantation of the device shown in FIG. 22A;

FIG. 23A is a cross sectional view in the first orientation, followingdeposition of a second spacer on the device shown in FIG. 22A;

FIG. 23B is a cross sectional view in the second orientationillustrating the deposition of the second spacer shown on the device ofFIG. 23A;

FIG. 24A is cross sectional view in the first orientation illustratingsource/drain ion implantation of the device shown in FIG. 23A;

FIG. 24B is a cross sectional view in the second orientationillustrating the source/drain implantation of the device shown in FIG.24A;

FIG. 25A is a cross sectional view in the first orientation, following aformation of a second SiO₂ hard mask on the device shown in FIG. 24A;

FIG. 25B is a cross sectional view in the second orientation, followingthe second SiO₂ hard mask formed on the device shown in FIG. 25B;

FIG. 26A is a cross sectional view in the first orientation followingremoval of the amorphous/polysilicon gate material to expose the gatepocket of the device illustrated in FIG. 25A;

FIG. 26B is a cross sectional view in the second orientation followingthe removal of the amorphous/polysilicon gate material the deviceillustrated in FIG. 26A;

FIG. 27A is a cross sectional view in the first orientation, following adeposition of high-k and metal gate material in the gate pocket of thedevice illustrated in FIG. 26A; and

FIG. 27B is cross sectional view in the second orientation of the high-kand metal gate material deposited in the gate pocket of the deviceillustrated in FIG. 27A.

FIG. 28 is a flow diagram illustrating a method of fabricating asemiconductor structure according to an exemplary embodiment of thepresent teachings; and

FIG. 29 is a flow diagram illustrating a method of fabricating asemiconductor structure according to another exemplary embodiment of thepresent teachings.

DETAILED DESCRIPTION

FIGS. 1A-1B illustrate a semiconductor structure 100 according to anexemplary embodiment. The semiconductor structure 100 includes asemiconductor substrate 102 generally indicated. The semiconductorsubstrate 102 may extend along an X-axis to define a length, and aY-axis perpendicular to the X-axis to define a width. The semiconductorsubstrate 102 may include a gate region 104 disposed between first andsecond non-gate regions 106/106′. In at least one exemplary embodiment,the first and second non-gate regions 106/106′ include first and secondsource/drain (S/D) regions. That is, the first non-gate region 106 maycorrespond to a source region and the second non-gate region 106′ maycorrespond to a drain region. The non-gate regions 106/106′ may alsoinclude regions identified as future source/drain regions to be effectedvia a future doping procedure, and/or regions that have alreadyundergone a doping procedure to effect S/D regions. Accordingly, thenon-gate regions 106/106′ will hereinafter be referred to as S/D regions106/106′.

Exemplary embodiments here on out illustrate the semiconductor substrate102 as a silicon-on-insulator (SOI) wafer. However, it can also beappreciated that other semiconductor substrates may be used. Forexample, the semiconductor substrate 102 may include, but is not limitedto, a bulk semiconductor substrate comprising silicon, germanium,silicon germanium, silicon carbide, or a III-V compound semiconductor(e.g., GaAs), and a II-VI compound semiconductors (e.g., ZnSe). Inaddition, an entire semiconductor substrate 102, or a portion thereof,may be amorphous, polycrystalline, or single-crystalline. Theaforementioned types of semiconductor substrates 102 may also include ahybrid oriented (HOT) semiconductor substrate, which provides surfaceregions of different crystallographic orientation. The semiconductorsubstrate 102 may be doped, undoped or contain doped regions and undopedregions therein. Further, the semiconductor substrate 102 may bestrained, unstrained, contain regions of strain and no strain therein,or contain regions of tensile strain and compressive strain.

FIGS. 1-14 illustrate a flow process of forming a semiconductorstructure 100, such as a FinFET device, according to an exemplaryembodiment of present teachings. Referring to FIG. 1B, the semiconductorsubstrate 102 may be formed as a silicon-on-insulator (SOI) wafer 108.The SOI wafer 108 includes a buried insulator layer 110 formed on a bulklayer (not shown), an active SOI layer 112 such as silicon, and amasking layer 114.

The buried insulator layer 110 may be a buried oxide (BOX) layer 110that separates and electrically isolates the bulk layer from the SOIlayer 112. The buried insulator layer 110 may have a thickness rangingfrom about 20 nanometers (nm) to about 200 nanometers (nm). The activeSOI layer 112 is disposed between the buried insulator layer 110 and themasking layer 114, and may have a thickness of about 30 nanometers (nm).The masking layer 114 is formed on an upper surface of the active SOIlayer 112 to provide a hardmask or covering. The masking layer 114 maybe made of a dielectric including, for example, silicon dioxide (SiO₂).

Referring to FIG. 2, a cross sectional view illustrates patterning ofthe masking layer 114 to form a gate pocket 116 formed in the gateregion 104. More specifically, the gate pocket 116 may be formed in thegate region 104 located between the first and second S/D regions106/106′, and through the masking layer 114, to expose the SOI layer112. The gate pocket 116 may extend through the masking layer 114 andstop at the active SOI layer 112. The gate pocket may also extendthrough the SOI layer 112, as discussed in greater detail below. Variousetching methods may be used to form the gate pocket 116 including, butnot limited to, sidewall image transfer (SIT) or pitch split processing.

FIG. 3 is a top view of the semiconductor substrate 102 of FIG. 2,following transfer of the masking layer 114 patterning into the SOIlayer 112 to define a plurality of semiconductor fins 118 in the gatepocket 116. Although a plurality of fins 118 is formed, a single fin maybe formed on the buried insulator layer 110. The fins 118 may be made ofa single crystal semiconductor shape, and may be formed to have bodiesof various shapes. For example, the fins 118 may have narrow fin bodiesextending parallel to the width of the substrate in the X-axisdirection, and sidewalls projecting vertically from the buried insulatorlayer. Further, the fins 118 may be made of single crystal semiconductormaterial.

The fins 118 may be formed using various conventional processesincluding, but not limited to, optical lithographic process, e-beamlithographic processes, trimming processes such as, for example, resisttrimming, hard mask trimming or oxidation trimming, and a combinationthereof. In at least one exemplary embodiment of the present teachings,the fins 118 are formed using a sidewall image transfer (SIT) process.

As illustrated in FIGS. 4A-4B, the plurality of fins 118 are formed inthe gate pocket 116 of the SOI wafer 108, and between the first andsecond S/D regions 106/106′. Accordingly, walls 119 formed by the gatepocket 116 may isolate the plurality of fins 118 from the first andsecond S/D regions 106/106′.

More specifically, FIG. 4A is a cross-sectional view of the SOI wafer108 illustrated in FIG. 3 taken along section A-A′. A single fin 118′among the plurality of fins 118 is illustrated in phantom. The fin 118′is formed in the gate pocket 116, and extends in a lengthwise directionalong the X-axis between the first and second S/D regions 106/106′ todefine a length thereof. The length of the fin 118 may range from about2 nanometers (nm) to about 50 nanometers (nm). In one embodiment, thelength of fin varies from 10 nm to 40 nm.

FIG. 4B is a cross-sectional view of the SOI wafer 108 taken alongsection B-B′ of the SOI wafer 108 illustrated in FIG. 3. The pluralityof fins 118 is arranged in an array that extends along the widthwisedirection of the SOI wafer 108, i.e., the Y-axis. Each single fin 118′extends along the Y-axis to define a width thereof. The width of eachfin 118′ may range from about 3 nanometers to about 20 nanometers.Further, a distance between each single fin 118′ in the Y-axis directiondefines a fin pitch. At least one exemplary embodiment provides a finpitch corresponding to the plurality of fins 118 ranging from about 8nanometers (nm) to about 50 nanometers (nm). Accordingly, by forming thefins 118 in the gate pocket 116 and between the first and second S/Dregions 106/106′, fin erosion during gate and spacer patterningprocesses may be avoided. Moreover, at least one exemplary embodiment ofthe present teachings provides forming fins 118 in only the gate pocket116 of the gate region 104, and not the S/D regions 106/106′. As aresult, an epitaxy (EPI) process for merging fins located in the S/Dregions may be eliminated as discussed in greater detail below.

Referring now to FIGS. 5A-5B, a spacer layer 120 may be disposed on themasking layer 114. More specifically, the spacer layer 120 may bedeposited on an upper surface of the masking layer 114, and into thegate pocket 116 to cover the plurality of fins 118. The spacer layer 120may be made, for example, of SiN. Thereafter, portions of the spacerlayer 120 may be etched away to expose upper surfaces of the maskinglayer 114, as illustrated in FIGS. 6A-6B. Further, the spacer layer 120may be etched away from the fins 118 and the surface of the gate pocket116 to expose the buried oxide layer 110. Various etching techniques maybe used to remove the spacer layer including, but not limited to,reactive-ion etching (RIE). Accordingly, the spacer layer 120 is left toremain on the wall 119 of the gate pocket 116 to define spacers 120′.

Referring now to FIGS. 7-14, a gate stack, i.e., gate, is formed in thegate pocket 116 of the SOI wafer 108 illustrated in FIGS. 6A-6B. Thegate may be formed using a variety of conventional methods including,but not limited to, a replacement metal gate process, i.e., gate-lastprocess.

As illustrated in FIGS. 7A-7B, for example, a dummy gate 122 may beformed in the gate pocket 116. The dummy gate 122 may be formed ofvarious material including, but not limited amorphous silicon andpolysilicon. The dummy gate 122 may also be etched such that it is flushwith the upper surface of the masking layer 114. Various methods foretching the dummy gate 122 may be used including, but not limited to,dry etching and chemical-mechanical polishing (CMP).

Additional procedures during the replacement metal gate process may beperformed on the semiconductor device 100. For example, the initialmasking layer 114 may be removed to expose the spacers 120′ disposedagainst the walls 119 of the gate pocket 116 as illustrated in FIGS.8A-8B. An extension of the initial spacers 120′ may be achieved byimplanting ions (+), as illustrated in FIGS. 9A-9B. FIGS. 10A-10Billustrated a second spacer 124 formed against the initial spacer 120′to protect gate region 104 during S/D region 106/106′ diffusion. Ionimplantation (+) to form the S/D regions 106/106′ is illustrated inFIGS. 11A-11B, and a new flowable oxide layer 114′ such as silicon oxide(SiO₂) may be formed on an upper surface of the semiconductor, and mayact as a new masking layer 114′ as illustrated in FIGS. 12A-12B.

Referring now to FIGS. 13A-13B, the dummy gate 122 may be removed, i.e.,pulled out, to re-expose the gate pocket 116, and a gate stack 126 maybe formed in the re-exposed gate pocket 116, as illustrated in FIG.14A-14B. The gate stack 126 may include a gate insulation layer 128 madeof a high dielectric constant (high-k) material. The high-k material mayinclude, but is not limited to, hafnium dioxide (HfO₂), hafnium siliconoxynitride (HfSiON), or zirconium dioxide (ZrO₂). The gate stack 126 mayfurther include a metal electrode 130 coupled to the insulation gatelayer to prevent Fermi-level pinning and increase electrical conductionat the gate stack 126. The metal electrode 130 may be formed of ametal-gate forming material including but not limited to, lanthanum(La), aluminum (Al), magnesium (Mg), ruthenium (Ru), titanium-basedmaterials such as titanium (Ti) and titanium nitride (TiN),tantalum-based materials such as tantalum (Ta) and tantalum nitride(TaN) or tantalum carbide (Ta₂C), or the like. The gate stack 126 may beplanarized using various processes including, but not limited to, CMP,such that the gate stack 126 is flush with new masking layer 114′.

Accordingly, FIGS. 14A-14B illustrate a fabricated semiconductorstructure 100, such as a FinFET device 200 according to at least oneexemplary embodiment of the present teachings. The FinFET device 200includes an SOI wafer 108 having a plurality of fins 118 formed in onlythe gate pocket 116 of the gate region 104, which is located between theS/D regions 106/106′. That is, no fins 118 are formed in the S/D regions106/106′. Therefore, the conventional process of epitaxially mergingfins formed in the S/D regions may be eliminated from the fabricationprocess, thereby reducing overall processing and material costs.Further, since the gate patterning is initially performed in preparationfor fin formation, the fins are prevented from being eroded during agate patterning process.

In addition to forming fins in a gate region of a semiconductorsubstrate without forming fins in the non-gate regions, the presentteachings allow for the formation of hanging fins and nanowire fins toproduce a semiconductor FinFET device having a reduced size.

Referring to FIGS. 15-27, block diagrams corresponding to a process flowof fabricating a semiconductor structure 100, such as a FinFET device300, are illustrated according to an exemplary embodiment of the presentteachings. The process flow of fabricating the FinFET device 300 issimilar to the process flow illustrated in FIGS. 1-14 discussed above.The FinFET device 300 includes an active SOI layer 112 formed between aburied insulation layer 110 and a masking layer 114.

In at least one exemplary embodiment illustrated in FIG. 15A-15B,however, the buried insulation layer 110 is recessed below the activeSOI layer 112 after forming the plurality of fins 118, thereby forming arecessed buried insulation region 302. After a spacer layer 120 isformed on the SOI substrate 108, and an etching procedure is performedto form spacers 120′, as illustrated in FIGS. 16-17 according to theprocesses described above, a portion of the buried insulation layer 110beneath the fins 118 is removed to form hanging fins 304, as illustratedin FIGS. 18A-18B. The hanging fins 304 are supported by walls 119 of thegate pocket 116, and are separated from the recessed buried insulationlayer 302 by a predetermined distance. For example, the hanging fins maybe separated from the recessed buried insulation layer by a distance ofabout 3 nanometers (nm) to about 20 nanometers (nm) such that a voidarea 306 is formed between a lower surface of the hanging fins 304 andthe recessed buried insulation layer 302. Similar to the teachingsdescribed above, the walls 119 of the gate pocket 116 may isolate thehanging fins 304 from the non-gate regions 106/106′, e.g., S/D regions,of the semiconductor structure 100.

The hanging fins 304 may undergo an annealing process that formsnanowire fins, i.e., nanowires 308, as illustrated in FIGS. 19A-19B.According to at least one exemplary embodiment of the present teachings,the nanowires 308 have a cylindrical shape, but are not limited thereto.That is, the nanowires 308 may have any shape that allows for reducingthe overall size of the semiconductor device 100. Furthermore, nanowiresmay be sized small enough that the resulting low density allows thenanowires to be considered as one-dimensional (1-D) nanostructures.Therefore, the dimensions of the nanowires 308 may be based on adiameter:length aspect ratio. According to at least one exemplaryembodiment of the present teachings, the nanowires 308 have adiameter:length aspect ratio of about 1:1. Due to the small diameter ofthe nanowires 308, the gate region 104 may be increased to cover alarger area of the semiconductor structure 100. For example, thesemiconductor device may be designed according to a wrap-gatearchitecture such that the gate region 104, and thus the nanowires 308,wrap completely around the semiconductor structure 100, as opposed toonly two gate regions offered by the traditional dual-gate FinFETarchitecture.

After the nanowires 308 are formed, the semiconductor device 100 mayundergo replacement metal gate procedure and S/D region formationaccording to the process described above to form the gate stack 126 inthe gate pocket 116 as illustrated in FIGS. 20-27.

Referring to FIG. 28, a flow diagram illustrates a method of fabricatinga semiconductor structure according to an exemplary embodiment of thepresent teachings. At operation 2800, a semiconductor substrate isformed. The semiconductor substrate may include a silicon-on-insulator(SOI). A gate pocket may be formed at a gate region of the semiconductorsubstrate at operation 2802. The gate pocket may extend through layersof the SOI substrate to expose an active silicon layer. At operation2804, semiconductor fins are formed in the gate pocket. The fins may besupported by walls of the gate pocket. Moreover, walls of the gatepocket may isolate the plurality of fins from non-gate regions of thesemiconductor substrate. For example, the gate pocket may isolate thefins from S/D regions of the semiconductor substrate. At operation 2806,the semiconductor substrate is oxidized to prepare the surface of thesubstrate for forming a spacer layer thereon. Accordingly, a spacerlayer is formed on the semiconductor device such that the fins arecovered. The spacer layer is removed from upper surfaces of thesubstrate and the fins at operation 2808, thereby leaving spacersdisposed against walls of the gate pocket.

At operation 2810, a gate material is deposited in the gate pocket,which covers the fins. The gate material may also undergochemical-mechanical polishing (CMP) procedure such that deposited gatematerial is flush with the upper surface of the semiconductor substrate.Flowable oxide, such as a silicon oxide (SiO₂) layer, which is disposedon the active silicon layer may be removed using conventional processesat operation 2812. At operation 2814, the semiconductor substrate mayundergo an ion implantation to increase the volume of the spacers, and asecond spacer may be formed against the extended spacer at operation2816. At operation 2818, ions are implanted in the non-gate regions toform S/D regions. That is, a first non-gate region existing at firstside of the gate region may be implanted with ions to form a sourceregion, and a second non-gate region located on an opposite side of thegate-region may be implanted with ions to form a drain region. A secondflowable oxide, such as SiO₂, is formed on an upper surface of thesemiconductor substrate at operation 2820. At operation 2822, the gatematerial deposited in the gate pocket is removed to re-expose the gatepocket and fins, and metal gate replacement process is performed suchthat a metal gate material different from the gate material utilized atoperation 2810 is deposited in the gate-pocket to cover the fins, andthe method ends.

Accordingly, fins may be formed in a gate region and between first andsecond S/D regions, without requiring fins to extend into the S/Dregions of the semiconductor structure. Since no fins exist in the S/Dregions, a merging procedure to merge the fins in the S/D regions isexcluded. Further, since no etching procedure is required to etch finsmerged in the S/D regions, erosion and damage of the fins existing inthe source/drain region caused by a merged-fin etching process isprevented.

Referring to FIG. 29, a flow diagram illustrates another method offabricating a semiconductor structure according to an exemplaryembodiment of the present teachings. The exemplary method illustrated inFIG. 29 is similar to method illustrated in FIG. 28 discussed in detailabove, but includes additional features of forming hanging fins andnanowires. More specifically, a semiconductor substrate, such as a SOIsubstrate, is formed and a gate pocket is formed at a gate region of thesubstrate at operations 2900 and 2902, respectively. At operation 2904,the gate pocket is recessed to form a recessed region in a layer of thesubstrate, for example the buried insulation layer. At operation 2906,semiconductor fins are formed in the gate pocket. The substrate and finsare oxidized and a spacer layer is formed thereon at operation 2908. Atoperation 2010, the spacer layer is partially removed to form spacers onthe walls of the gate pocket. Turning now to operation 2912, a portionof the substrate located beneath the fins is removed to form hangingfins. Accordingly, a void area is defined between the recessed layer ofthe gate pocket and the plurality of fins such that a plurality ahanging fins are formed. The hanging fins undergo an annealing processat operation 2914, which transforms the hanging fins into nanowire fins,i.e., nanowires. A dummy gate is formed at operation 2916 by depositingan amorphous and/or polysilicon in the gate pocket at operation 2916. Atoperation 2918 the initial hardmask layer may be removed, and thespacers may be extended via ion implantation at operation 2920. A secondspacer may be disposed against each of the initial spacers at operation2922. At operation 2924, the source/drain regions may be formed via ionimplantation and a second hardmask may be formed on an upper surface ofthe substrate at operation 2926. At operation 2928, a replacement metalgate process may be performed to form a metal gate in the gate pocket,and method ends. By forming nanowires in the gate pocket, the gateregion of the semiconductor structure may be increased to cover a largerarea of the semiconductor structure. Therefore, the overall size of thesemiconductor structure may be reduced.

The terminology used herein is for the purpose of describing exemplaryembodiments only and is not intended to be limiting of the teachings. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of onemore other features, integers, steps, operations, element components,and/or groups thereof.

The flow diagrams depicted herein are just one example. There may bemany variations to this diagram or operations described therein withoutdeparting from the spirit of the teachings. For instance, the operationsmay be performed in a differing order or operations may be added,deleted or modified. All of these variations are considered a part ofthe claimed teachings.

While exemplary embodiments to the present teachings have beendescribed, it will be understood that those skilled in the art, both nowand in the future, may make various changes the teachings which fallwithin the scope of the claims described below.

1. A method of forming a semiconductor device having first and secondnon-gate regions, the method comprising: forming an active semiconductorlayer disposed on an insulation layer; forming a gate pocket through theactive semiconductor layer and the insulation layer to define a recessedgate insulation region between the first and second non-gate regions;forming a plurality of fins supported by walls of the gate pocket; andremoving a portion of the recessed gate insulation region locatedbeneath the plurality of fins to define a void between each fin amongthe plurality of fins and the recessed gate insulation region.
 2. Themethod of claim 1, further comprising extending the recessed gateinsulation region below the insulation layer at a predetermined depth.3. The method of claim 2, further comprising forming a masking layer onan upper surface of the active semiconductor layer, and extending thegate pocket from an upper surface of the masking layer to the recessgate insulation region.
 4. The method of claim 3, further comprisingarranging the plurality of fins sequentially in the gate pocket.
 5. Themethod of claim 4, further comprising extending the gate insulationlayer along a first direction to define a gate length, and forming eachfin among the plurality of fins along the first direction to define afin length not exceeding the gate length.
 6. The method claim 5, furthercomprising forming a gate stack in the gate pocket to cover theplurality of fins.
 7. The method of claim 1, further comprisingannealing the plurality of fins to form a plurality of nanowires.